diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index 2f923f2..3f5eeb7 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -318,19 +318,19 @@
 	u16 ctrl, oldctrl;
 
 	do {
-		eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl);
-		oldctrl = ctrl & PHY_BMCR_AUTON;
+		eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl);
+		oldctrl = ctrl & BMCR_ANENABLE;
 
-		ctrl ^= PHY_BMCR_AUTON;
-		eth_mdio_write(dev, phy_addr, PHY_BMCR, ctrl);
-		eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl);
-		ctrl &= PHY_BMCR_AUTON;
+		ctrl ^= BMCR_ANENABLE;
+		eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl);
+		eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl);
+		ctrl &= BMCR_ANENABLE;
 
 		if (ctrl == oldctrl) {
 			phy_addr++;
 		} else {
-			ctrl ^= PHY_BMCR_AUTON;
-			eth_mdio_write(dev, phy_addr, PHY_BMCR, ctrl);
+			ctrl ^= BMCR_ANENABLE;
+			eth_mdio_write(dev, phy_addr, MII_BMCR, ctrl);
 
 			return phy_addr;
 		}
@@ -347,10 +347,10 @@
 	int timeout = CONFIG_PHYRESET_TIMEOUT;
 	u32 phy_addr = priv->address;
 
-	eth_mdio_write(dev, phy_addr, PHY_BMCR, PHY_BMCR_RESET);
+	eth_mdio_write(dev, phy_addr, MII_BMCR, BMCR_RESET);
 	do {
-		eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl);
-		if (!(ctrl & PHY_BMCR_RESET))
+		eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl);
+		if (!(ctrl & BMCR_RESET))
 			break;
 		udelay(1000);
 	} while (timeout--);
@@ -386,33 +386,33 @@
 		return -1;
 
 #if defined(CONFIG_DW_AUTONEG)
-	bmcr = PHY_BMCR_AUTON | PHY_BMCR_RST_NEG | PHY_BMCR_100MB | \
-	       PHY_BMCR_DPLX | PHY_BMCR_1000_MBPS;
+	bmcr = BMCR_ANENABLE | BMCR_ANRESTART | BMCR_SPEED100 | \
+	       BMCR_FULLDPLX | BMCR_SPEED1000;
 #else
-	bmcr = PHY_BMCR_100MB | PHY_BMCR_DPLX;
+	bmcr = BMCR_SPEED100 | BMCR_FULLDPLX;
 
 #if defined(CONFIG_DW_SPEED10M)
-	bmcr &= ~PHY_BMCR_100MB;
+	bmcr &= ~BMCR_SPEED100;
 #endif
 #if defined(CONFIG_DW_DUPLEXHALF)
-	bmcr &= ~PHY_BMCR_DPLX;
+	bmcr &= ~BMCR_FULLDPLX;
 #endif
 #endif
-	if (eth_mdio_write(dev, phy_addr, PHY_BMCR, bmcr) < 0)
+	if (eth_mdio_write(dev, phy_addr, MII_BMCR, bmcr) < 0)
 		return -1;
 
 	/* Read the phy status register and populate priv structure */
 #if defined(CONFIG_DW_AUTONEG)
 	timeout = CONFIG_AUTONEG_TIMEOUT;
 	do {
-		eth_mdio_read(dev, phy_addr, PHY_BMSR, &bmsr);
-		if (bmsr & PHY_BMSR_AUTN_COMP)
+		eth_mdio_read(dev, phy_addr, MII_BMSR, &bmsr);
+		if (bmsr & BMSR_ANEGCOMPLETE)
 			break;
 		udelay(1000);
 	} while (timeout--);
 
-	eth_mdio_read(dev, phy_addr, PHY_ANLPAR, &anlpar);
-	eth_mdio_read(dev, phy_addr, PHY_1000BTSR, &btsr);
+	eth_mdio_read(dev, phy_addr, MII_LPA, &anlpar);
+	eth_mdio_read(dev, phy_addr, MII_STAT1000, &btsr);
 
 	if (btsr & (PHY_1000BTSR_1000FD | PHY_1000BTSR_1000HD)) {
 		priv->speed = SPEED_1000M;
@@ -421,28 +421,28 @@
 		else
 			priv->duplex = HALF_DUPLEX;
 	} else {
-		if (anlpar & PHY_ANLPAR_100)
+		if (anlpar & LPA_100)
 			priv->speed = SPEED_100M;
 		else
 			priv->speed = SPEED_10M;
 
-		if (anlpar & (PHY_ANLPAR_10FD | PHY_ANLPAR_TXFD))
+		if (anlpar & (LPA_10FULL | LPA_100FULL))
 			priv->duplex = FULL_DUPLEX;
 		else
 			priv->duplex = HALF_DUPLEX;
 	}
 #else
-	if (eth_mdio_read(dev, phy_addr, PHY_BMCR, &ctrl) < 0)
+	if (eth_mdio_read(dev, phy_addr, MII_BMCR, &ctrl) < 0)
 		return -1;
 
-	if (ctrl & PHY_BMCR_DPLX)
+	if (ctrl & BMCR_FULLDPLX)
 		priv->duplex = FULL_DUPLEX;
 	else
 		priv->duplex = HALF_DUPLEX;
 
-	if (ctrl & PHY_BMCR_1000_MBPS)
+	if (ctrl & BMCR_SPEED1000)
 		priv->speed = SPEED_1000M;
-	else if (ctrl & PHY_BMCR_100_MBPS)
+	else if (ctrl & BMCR_SPEED100)
 		priv->speed = SPEED_100M;
 	else
 		priv->speed = SPEED_10M;